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ispGDX 80VA
TM
In-System Programmable 3.3V Generic Digital Crosspoint
TM
Features
* IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY -- Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement -- "Any Input to Any Output" Routing -- Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation -- Space-Saving PQFP and BGA Packaging -- Dedicated IEEE 1149.1-Compliant Boundary Scan Test * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 3.3V Core Power Supply -- 3.5ns Input-to-Output/3.5ns Clock-to-Output Delay -- 250MHz Maximum Clock Frequency -- TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable) -- Low-Power: 16.5mA Quiescent Icc -- 24mA IOL Drive with Programmable Slew Rate Control Option -- PCI Compatible Drive Capability -- Schmitt Trigger Inputs for Noise Immunity -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology * ispGDXVTM OFFERS THE FOLLOWING ADVANTAGES -- 3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP) -- Change Interconnects in Seconds * FLEXIBLE ARCHITECTURE -- Combinatorial/Latched/Registered Inputs or Outputs -- Individual I/O Tri-state Control with Polarity Control -- Dedicated Clock/Clock Enable Input Pins (two) or Programmable Clocks/Clock Enables from I/O Pins (20) -- Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns) -- Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX -- Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins -- Outputs Tri-state During Power-up ("Live Insertion" Friendly) * DESIGN SUPPORT THROUGH LATTICE'S ispGDX DEVELOPMENT SOFTWARE -- MS Windows or NT / PC-Based or Sun O/S -- Easy Text-Based Design Entry -- Automatic Signal Routing -- Program up to 100 ISP Devices Concurrently -- Simulator Netlist Generation for Easy Board-Level Simulation
Functional Block Diagram
I/O Pins D
ISP Control
I/O Pins C
I/O Pins A
I/O Cells
Global Routing Pool (GRP)
I/O Cells
Boundary Scan Control
I/O Pins B
Description
The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including: * Multi-Port Multiprocessor Interfaces * Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX) * Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.) * Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns. The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP). All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the required I/O outputs. I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs
Copyright (c) 2000 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8037; http://www.latticesemi.com
September 2000
gdx80VA_02
1
Specifications ispGDX80VA
Description (Continued)
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clock (CLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs. Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output. A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns. OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins. Optional dedicated clock input pins give minimum clockto-output delays. CLK and CLKEN share the same set of I/O pins. CLKEN disables the register clock when CLKEN = 0. Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined. In keeping with its data path application focus, the ispGDXVA devices contain no programmable logic arrays. All input pins include Schmitt trigger buffers for noise immunity. These connections are programmed into the device using non-volatile E2CMOS technology. Non-volatile technology means the device configuration is saved even when the power is removed from the device. Table 1. ispGDXVA Family Members
ispGDXV/VA Device ispGDX80VA I/O Pins I/O-OE Inputs* I/O-CLK / CLKEN Inputs* I/O-MUXsel1 Inputs* I/O-MUXsel2 Inputs* Dedicated Clock Pins** EPEN TOE BSCAN Interface RESET Pin Count/Package 80 20 20 20 20 2 1 1 4 1 100-Pin TQFP ispGDX160V/VA 160 40 40 40 40 4 1 1 4 1 ispGDX240VA 240 60 60 60 60 4 1 1 4 1
In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing. That is, any I/O pin configured as an input can drive one or more I/O pins configured as outputs. The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode). Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive. On the ispGDXVA, each I/O pin is individually programmable for 3.3V or 2.5V output levels as described later. Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise. All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability. In addition, in-system programming is supported through the Test Access Port via a special set of private commands. The ispGDXVA I/Os are designed to withstand "live insertion" system environments. The I/O buffers are disabled during power-up and power-down cycles. When designing for "live insertion," absolute maximum rating conditions for the Vcc and I/O pins must still be met.
208-Pin PQFP 388-Ball fpBGA 208-Ball fpBGA 272-Ball BGA
* The CLK/CLK_EN, OE, MUX0 and MUX1 terminals on each I/O cell can each be assigned to 25% of the I/Os. ** Global clock pins Y0, Y1, Y2 and Y3 are multiplexed with CLKEN0, CLKEN1, CLKEN2 and CLKEN3 respectively in all devices.
2
Specifications ispGDX80VA
Architecture
The ispGDXVA architecture is different from traditional PLD architectures, in keeping with its unique application focus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks/Clock Enables and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell. Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. In-system programming is accomplished through the standard Boundary Scan protocol. The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped together with one group per side.
I/O Architecture
Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines as well as a 4x4 crossbar switch controlled by software for increased routing flexiability (Figure 1). The four data inputs to the MUX (called M0, M1, M2, and M3) come from I/O signals in the GRP and/or adjacent I/O cells. Each MUX data input can access one quarter of the total I/Os. For example, in an 80-I/O ispGDXVA, each data input can connect to one of 20 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2. Each MUXsel input covers 25% of the total I/O pins (e.g. 20 out of 80). MUX0 and MUX1 can be driven from either MUXsel1 or MUXsel2.
Figure 1. ispGDXVA I/O Cell and GRP Detail (80 I/O Device)
Logic "0" Logic "1"
80 I/O Inputs
I/OCell 0
I/O Cell 79
I/O Cell 1
I/O Cell 78
E2CMOS Programmable Interconnect
From MUX Outputs of 2 Adjacent I/O Cells N+2 I/O Group A I/O Group B I/O Group C I/O Group D N+1 4x4 Crossbar Switch
* * *
To 2 Adjacent I/O Cells above
Bypass Option
Register or Latch
4-to-1 MUX
M0 M1 M2 M3 MUX0 MUX1 To 2 Adjacent I/O Cells below
Prog. Prog. Pull-up Bus Hold Latch (VCCIO)
A B D CLK
CLK_EN Reset
C R
Prog. Open Drain 2.5V/3.3V Output Prog. Slew Rate
I/O Pin
Q
N-1 N-2
* * * * * *
From MUX Outputs of 2 Adjacent I/O Cells
Boundary Scan Cell
I/O Cell N
* * *
I/O Cell 38
******
I/O Cell 41
I/O Cell 39
40 I/O Cells 80 Input GRP
Inputs Vertical Outputs Horizontal Global Y0-Y3 Reset Global Clocks / Clock_Enables
I/O Cell 40
40 I/O Cells
ispGDXVA architecture enhancements over ispGDX (5V)
3
Specifications ispGDX80VA
I/O MUX Operation
MUX1 0 0 1 1 MUX0 0 1 1 0 Data Input Selected M0 M1 M2 M3
allow adjacent I/O cell outputs to be directly connected without passing through the global routing pool. The relationship between the [N+i] adjacent cells and A, B, C and D inputs will vary depending on where the I/O cell is located on the physical die. The I/O cells can be grouped into "normal" and "reflected" I/O cells or I/O "hemispheres." These are defined as:
Device ispGDX80VA ispGDX160V/VA ispGDX240VA Normal I/O Cells B9-B0, A19-A0, D19-D10 B19-B0, A39-A0, D39-D20 B29-B0, A59-A0, D59-D30 Reflected I/O Cells B10-B19, C0-C19, D0-D9 B20-B39, C0-C39, D0-D19 B30-B59, C0-C59, D0-D29
Flexible mapping of MUXselx to MUXx allows the user to change the MUX select assignment after the ispGDXVA device has been soldered to the board. Figure 1 shows that the I/O cell can accept (by programming the appropriate fuses) inputs from the MUX outputs of four adjacent I/O cells, two above and two below. This enables cascading of the MUXes to enable wider (up to 16:1) MUX implementations. The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when the input control MUX of the register/ latch selects the "A" path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the "B" path, the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity Clock to the latch or register can be connected to any I/O in the I/O-CLK/CLKEN set (onequarter of total I/Os) or to one of the dedicated clock input pins (Yx). The programmable polarity Clock Enable input to the register can be programmed to connect to any of the I/O-CLK/CLKEN input pin set or to the global clock enable inputs (CLKENx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Combinatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell output polarity can be programmed as active high or active low.
Table 2 shows the relationship between adjacent I/O cells as well as their relationship to direct MUX inputs. Note that the MUX expansion is circular and that I/O cell B10, for example, draws on I/Os B9 and B8, as well as B11 and B12, even though they are in different hemispheres of the physical die. Table 2 shows some typical cases and all boundary cases. All other cells can be extrapolated from the pattern shown in the table. Figure 2. I/O Hemisphere Configuration of ispGDX80VA
I/O cell 0 I/O cell 79
D19
D10
D9
D0
I/O cell index increases in this direction
C19
MUX Expander Using Adjacent I/O Cells
The ispGDXVA allows adjacent I/O cell MUXes to be cascaded to form wider input MUXes (up to 16 x 1) without incurring an additional full Tpd penalty. However, there are certain dependencies on the locality of the adjacent MUXes when used along with direct MUX inputs.
B0
B9
I/O cell 39
B10
I/O cell 40
B19
Adjacent I/O Cells
Expansion inputs MUXOUT[n-2], MUXOUT[n-1], MUXOUT[n+1], and MUXOUT[n+2] are fuse-selectable for each I/O cell MUX. These expansion inputs share the same path as the standard A, B, C and D MUX inputs, and
Direct and Expander Input Routing
Table 2 also illustrates the routing of MUX direct inputs that are accessible when using adjacent I/O cells as inputs. Take I/O cell D13 as an example, which is also shown in Figure 3.
4
C0
I/O cell index increases in this direction
A0 A19
Specifications ispGDX80VA
Figure 3. Adjacent I/O Cells vs. Direct Input Path for ispGDX80VA, I/O D13
ispGDX80VA I/O Cell I/O Group A D11 MUX Out I/O Group B D12 MUX Out I/O Group C D14 MUX Out I/O Group D D15 MUX Out 4x4 Crossbar Switch S1 S0
.m0 .m1 .m2 .m3
Special Features Slew Rate Control
All output buffers contain a programmable slew rate control that provides software-selectable slew rate options.
Open Drain Control
D13
It can be seen from Figure 3 that if the D11 adjacent I/O cell is used, the I/O group "A" input is no longer available as a direct MUX input. The ispGDXVA can implement MUXes up to 16 bits wide in a single level of logic, but care must be taken when combining adjacent I/O cell outputs with direct MUX inputs. Any particular combination of adjacent I/O cells as MUX inputs will dictate what I/O groups (A, B, C or D) can be routed to the remaining inputs. By properly choosing the adjacent I/O cells, all of the MUX inputs can be utilized. Table 2. Adjacent I/O Cells (Mapping of ispGDX80VA)
Data A/ Data B/ Data C/ Data D/ MUXOUT MUXOUT MUXOUT MUXOUT B10 B11 B12 Reflected I/O Cells B13 D6 D7 D8 D9 D10 D11 D12 Normal I/O Cells D13 B6 B7 B8 B9 B12 B13 B14 B15 D8 D9 D10 D11 D8 D9 D10 D11 B4 B5 B6 B7 B11 B12 B13 B14 D7 D8 D9 D10 D9 D10 D11 D12 B5 B6 B7 B8 B9 B10 B11 B12 D5 D6 D7 D8 D11 D12 D13 D14 B7 B8 B9 B10 B8 B9 B10 B11 D4 D5 D6 D7 D12 D13 D14 D15 B8 B9 B10 B11
All output buffers provide a programmable Open-Drain option which allows the user to drive system level reset, interrupt and enable/disable lines directly without the need for an off-chip Open-Drain or Open-Collector buffer. Wire-OR logic functions can be performed at the printed circuit board level.
Pull-up Resistor
All pins have a programmable active pull-up. A typical resistor value for the pull-up ranges from 50k to 80k.
Output Latch (Bus Hold)
All pins have a programmable circuit that weakly holds the previously driven state when all drivers connected to the pin (including the pin's output driver as well as any other devices connected to the pin by external bus) are tristated.
User-Programmable I/Os
The ispGDX80VA features user-programmable I/Os supporting either 3.3V or 2.5V output voltage level options. The ispGDX80VA uses a VCCIO pin to provide the 2.5V reference voltage when used.
PCI Compatible Drive Capability
The ispGDX80VA supports PCI compatible drive capability for all I/Os.
5
Specifications ispGDX80VA
Applications
The ispGDXVA Family architecture has been developed to deliver an in-system programmable signal routing solution with high speed and high flexibility. The devices are targeted for three similar but distinct classes of endsystem applications:
Programmable Switch Replacement (PSR)
Includes solid-state replacement and integration of mechanical DIP Switch and jumper functions. Through in-system programming, pins of the ispGDXVA devices can be driven to HIGH or LOW logic levels to emulate the traditional device outputs. PSR functions do not require any input pin connections. These applications actually require somewhat different silicon features. PRSI functions require that the device support arbitrary signal routing on-chip between any two pins with no routing restrictions. The routing connections are static (determined at programming time) and each input-to-output path operates independently. As a result, there is little need for dynamic signal controls (OE, clocks, etc.). Because the ispGDXVA device will interface with control logic outputs from other components (such as ispLSI or ispMACH) on the board (which frequently change late in the design process as control logic is finalized), there must be no restrictions on pin-to-pin signal routing for this type of application. PDP functions, on the other hand, require the ability to dynamically switch signal routing (MUXing) as well as latch and tri-state output signals. As a result, the programmable interconnect is used to define possible signal routes that are then selected dynamically by control signals from an external MPU or control logic. These functions are usually formulated early in the conceptual design of a product. The data path requirements are driven by the microprocessor, bus and memory architecture defined for the system. This part of the design is the earliest portion of the system design frozen, and will not usually change late in the design because the result would be total system and PCB redesign. As a result, the ability to accommodate arbitrary any pin-to-any pin rerouting is not a strong requirement as long as the designer has the ability to define his functions with a reasonable degree of freedom initially. As a result, the ispGDXVA architecture has been defined to support PSR and PRSI applications (including bidirectional paths) with no restrictions, while PDP applications (using dynamic MUXing) are supported with a minimal number of restrictions as described below. In this way, speed and cost can be optimized and the devices can still support the system designer's needs. The following diagrams illustrate several ispGDXVA applications.
Programmable, Random Signal Interconnect (PRSI)
This class includes PCB-level programmable signal routing and may be used to provide arbitrary signal swapping between chips. It opens up the possibilities of programmable system hardware. It is characterized by the need to provide a large number of 1:1 pin connections which are statically configured, i.e., the pin-to-pin paths do not need to change dynamically in response to control inputs.
Programmable Data Path (PDP)
This application area includes system data path transceiver, MUX and latch functions. With today's 32- and 64-bit microprocessor buses, but standard data path glue components still relegated primarily to eight bits, PCBs are frequently crammed with a dozen or more data path glue chips that use valuable real estate. Many of these applications consist of "on-board" bus and memory interfaces that do not require the very high drive of standard glue functions but can benefit from higher integration. Therefore, there is a need for a flexible means to integrate these on-board data path functions in an analogous way to programmable logic's solution to control logic integration. Lattice's CPLDs make an ideal control logic complement to the ispGDXVA in-system programmable data path devices as shown below. Figure 4. ispGDXVA Complements Lattice CPLDs
Address Inputs (from P) Control Inputs (from P) Data Path Bus #1 ISP/JTAG Interface
State Machines
Buffers / Registers Control Outputs
ispLSI/ ispMACH Device
Decoders
ispGDXVA Device
Buffers / Registers Configuration (Switch) Outputs
System Clock(s)
Data Path Bus #2
6
Specifications ispGDX80VA
Applications (Continued)
Figure 5. Address Demultiplex/Data Buffering
Designing with the ispGDXVA
As mentioned earlier, this architecture satisfies the PRSI class of applications without restrictions: any I/O pin as a single input or bidirectional can drive any other I/O pin as output. For the case of PDP applications, the designer does have to take into consideration the limitations on pins that can be used as control (MUX0, MUX1, OE, CLK) or data (MUXA-D) inputs. The restrictions on control inputs are not likely to cause any major design issues because the input possibilities span 25% of the total pins. The MUXA-D input partitioning requires that designers consciously assign pinouts so that MUX inputs are in the appropriate, disjoint groups. For example, since the MUXA group includes I/O A0-A19 (80 I/O device), it is not possible to use I/O A0 and I/O A9 in the same MUX function. As previously discussed, data path functions will be assigned early in the design process and these restrictions are reasonable in order to optimize speed and cost.
Data Bus B
XCVR I/OA I/OB
MUXed Address Data Bus
Buffered Data
OEA
OEB To Memory/ Peripherals
Control Bus
Address Latch D Q Address
CLK
Figure 6. Data Bus Byte Swapper
D0-7 XCVR I/OA I/OB D0-7 XCVR I/OA I/OB
OEA OEB
Data Bus A
User Electronic Signature
The ispGDXVA Family includes dedicated User Electronic Signature (UES) E2CMOS storage to allow users to code design-specific information into the devices to identify particular manufacturing dates, code revisions, or the like. The UES information is accessible through the boundary scan programming port via a specific command. This information can be read even when the security cell is programmed.
OEA OEB XCVR D8-15 I/OA I/OB D8-15 XCVR I/OA I/OB
Control Bus
OEA OEB
OEA OEB
Security
Figure 7. Four-Port Memory Interface
4-to-1 16-Bit MUX Bidirectional Port #1 OE1 Port #2 OE2 Port #3 OE3
Bus 2
The ispGDXVA Family includes a security feature that prevents reading the device program once set. Even when set, it does not inhibit reading the UES or device ID code. It can be erased only via a device bulk erase.
To Memory
Memory Port OEM
Bus 4
Bus 3
SEL0
Note: All OE and SEL lines driven by external arbiter logic (not shown).
Bus 1
Port #4 OE4
SEL1
7
Specifications ispGDX80VA
Absolute Maximum Ratings 1,2
Supply Voltage Vcc ................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement.
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage I/O Reference Voltage Commercial Industrial TA = 0C to +70C TA = -40C to +85C MIN. 3.00 3.00 2.3 MAX. 3.60 3.60 3.60 UNITS V V V
Table 2-0005/gdxva
VCC VCCIO
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER I/O Capacitance Dedicated Clock Capacitance PACKAGE TYPE TQFP TQFP TYPICAL 7 8 UNITS pf pf TEST CONDITIONS VCC = 3.3V, VI/O = 2.0V VCC = 3.3V, VY = 2.0V
Table 2-0006/gdxva
C1 C2
Erase/Reprogram Specifications
PARAMETER Erase/Reprogram Cycles MINIMUM 10,000 MAXIMUM -- UNITS Cycles
8
Specifications ispGDX80VA
Switching Test Conditions
Figure 8. Test Load
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to VCCIO(MIN) < 1.5ns 10% to 90% VCCIO(MIN)/2 VCCIO(MIN)/2 See Figure 8
VCCIO R1 Device Output R2 CL* Test Point
3-state levels are measured 0.5V from steady-state active level.
Output Load Conditions (See Figure 8)
3.3V TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL+0.5V Slow Slew R1 153 R2 134 134 R1 156 2.5V R2 CL 144 35pF 144 35pF
*CL includes Test Fixture and Probe Capacitance.
0213D
153
156
134
144
35pF 5pF 5pF 35pF
153
156
C D

Table 2-0004A/gdxva
DC Electrical Characteristics for 3.3V Range
Over Recommended Operating Conditions
SYMBOL PARAMETER I/O Reference Voltage Input Low Voltage Input High Voltage Output Low Voltage CONDITION - VOH VOUT or VOUT VOL (MAX) VOH VOUT or VOUT VOL(MAX) VCC = VCC (MIN) VCC = VCC (MIN) IOL = +100A IOL = +24mA IOH = -100A IOH = -12mA MIN. 3.0 -0.3 2.0 - - 2.8 2.4 TYP. - - - - - - -
1
MAX. UNITS 3.6 0.8 5.25 0.2 0.55 - - V V V V V V V
VCCIO VIL VIH VOL VOH
Output High Voltage
1. Typical values are at VCC = 3.3V and TA = 25C.
Table 2-0007/gdxva
9
Specifications ispGDX80VA
DC Electrical Characteristics for 2.5V Range
Over Recommended Operating Conditions
SYMBOL PARAMETER I/O Reference Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CONDITION - VOH(MIN) VOUT or VOUT VOL(MAX) VOH(MIN) VOUT or VOUT VOL(MAX)
VCCIO=MIN, IOL = 100A VCCIO=MIN, IOL = 8mA VCCIO=MIN, IOH = -100A VCCIO=MIN, IOH = -8mA
MIN. 2.3 -0.3 1.7 - - 2.1 1.8
TYP. - - - - - - -
MAX. UNITS 2.7 0.7 5.25 0.2 0.6 - - V V V V V V V
2.5V/gdxva
VCCIO VIL VIH VOL VOH
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Input or I/O Low Leakage Current Input or I/O High Leakage Current I/O Active Pullup Current Bus Hold Low Sustaining Current Bus Hold High Sustaining Current Bus Hold Low Overdrive Current Bus Hold High Overdrive Current Bus Hold Trip Points Output Short Circuit Current Quiescent Power Supply Current Dynamic Power Supply Current per Input Switching Maximum Continuous I/O Pin Sink Current Through Any GND Pin CONDITION 0V VIN VIL (MAX) (VCCIO-0.2) VIN VCCIO VCCIO VIN 5.25V 0V VIN VIL (MAX) VIN = VIL (MAX) VIN = VIH (MIN) 0V VIN VCCIO 0V VIN VCCIO VCC = 3.3V, VOUT = 0.5V, TA = 25C VIL = 0.5V, VIH = VCC One input toggling at 50% duty cycle, outputs open. - MIN. - - - - 40 -40 - - VIL - - - TYP.2 - - - - - - - - - - 12 See Note 3 - MAX. -10 10 50 -200 - - 550 -550 VIH -250 - - UNITS A A A A A A A A V mA mA mA/ MHz mA
IIL IIH IPU IBHLS IBHHS IBHLO IBHHO IBHT IOS1 ICCQ4 ICC ICONT 5
-
160
DC Char_gdx80VA 1. One output at a time for a maximum of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized, but not 100% tested. 2. Typical values are at VCC = 3.3V and TA = 25C. 3. ICC / MHz = (0.002 x I/O cell fanout) + 0.022. e.g. An input driving four I/O cells at 40MHz results in a dynamic ICC of approximately ((0.002 x 4) + 0.022) x 40 = 1.20mA. 4. For a typical application with 50% of I/O pins used as inputs, 50% used as outputs or bi-directionals. 5. This parameter limits the total current sinking of I/O pins surrounding the nearest GND pin.
10
Specifications ispGDX80VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1 PARAMETER COND. #
-3
DESCRIPTION - - 250
1 tsu3+tgco1
-5
3.5 3.5 - - - - - - - - - - - - - - - - 3.5 6.0 4.0 7.0 5.0 5.0 6.0 6.0 - - 8.0 - 3.5 - - 143 111 4.0 3.0 4.0 3.0 2.5 1.5 4.5 0.0 1.5 0.0 1.5 0.0 1.5 0.0 - - - - - - - - 3.5 3.5 - 10.0 - 5.0 5.0 - - - - - - - - - - - - - - - - 5.0 8.5 6.0 9.5 6.0 6.0 6.0 6.0 - - 14.0 - 5.0
UNITS ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX.
ns 0.5 - 0.5 - A 32 Output Skew (tgco1 Across Chip) 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference.
tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk
A A - - - - - - - - - - - - - - - - A A A A B C B C - - - - D
1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) 3 Clock Frequency, Max. Toggle 4 Clock Frequency with External Feedback (
)
166.7 3.0 2.5 2.5 2.0 2.5 1.5 3.0 0.0 0.5 0.0 1.0 0.0 1.0 0.0 - - - - - - - - 2.0 2.0 - 5.0 -
5 Input Latch or Register Setup Time Before Yx 6 Input Latch or Register Setup Time Before I/O Clock 7 Output Latch or Register Setup Time Before Yx 8 Output Latch or Register Setup Time Before I/O Clock 9 Global Clock Enable Setup Time Before Yx 10 Global Clock Enable Setup Time Before I/O Clock 11 I/O Clock Enable Setup Time Before Yx 12 Input Latch or Reg. Hold Time (Yx) 13 Input Latch or Reg. Hold Time (I/O Clock) 14 Output Latch or Reg. Hold Time (Yx) 15 Output Latch or Reg. Hold Time (I/O Clock) 16 Global Clock Enable Hold Time (Yx) 17 Global Clock Enable Hold Time (I/O Clock) 18 I/O Clock Enable Hold Time (Yx) 19 Output Latch or Reg. Clock (from Yx) to Output Delay 20 Input Latch or Register Clock (from Yx) to Output Delay 21 Output Latch or Register Clock (from I/O pin) to Output Delay 22 Input Latch or Register Clock (from I/O pin) to Output Delay 23 Input to Output Enable 24 Input to Output Disable 25 Test OE Output Enable 26 Test OE Output Disable 27 Clock Pulse Duration, High 28 Clock Pulse Duration, Low 29 Register Reset Delay from RESET Low 30 Reset Pulse Width 31 Output Delay Adder for Output Timings Using Slow Slew Rate
11
Specifications ispGDX80VA
External Timing Parameters
Over Recommended Operating Conditions
TEST1 PARAMETER COND. #
-7
DESCRIPTION - - 100
1 tsu3+tgco1
-9
7.0 7.0 - - - - - - - - - - - - - - - - 7.0 11.0 9.0 13.0 8.5 8.5 8.5 8.5 - - 18.0 - 7.0 - - 83 62.5 7.0 6.0 7.0 6.0 4.0 3.0 8.5 0.0 3.0 0.0 3.0 0.0 3.0 0.0 - - - - - - - - 6.0 6.0 - 18.0 - 9.0 9.0 - - - - - - - - - - - - - - - - 9.0 13.5 11.5 15.7 10.5 10.5 10.5 10.5 - - 22.0 - 9.0
UNITS ns ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX.
ns 1.0 - A 32 Output Skew (tgco1 Across Chip) - 0.5 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference.
tpd2 tsel2 fmax (Tog.) fmax (Ext.) tsu1 tsu2 tsu3 tsu4 tsuce1 tsuce2 tsuce3 th1 th2 th3 th4 thce1 thce2 thce3 tgco12 tgco22 tco12 tco22 ten2 tdis2 ttoeen2 ttoedis2 twh twl trst trw tsl tsk
A A - - - - - - - - - - - - - - - - A A A A B C B C - - - - D
1 Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX) 2 Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX) 3 Clock Frequency, Max. Toggle 4 Clock Frequency with External Feedback (
)
80 5.5 4.5 5.5 4.5 3.5 2.5 6.5 0.0 2.5 0.0 2.5 0.0 2.5 0.0 - - - - - - - - 5.0 5.0 - 14.0 -
5 Input Latch or Register Setup Time Before Yx 6 Input Latch or Register Setup Time Before I/O Clock 7 Output Latch or Register Setup Time Before Yx 8 Output Latch or Register Setup Time Before I/O Clock 9 Global Clock Enable Setup Time Before Yx 10 Global Clock Enable Setup Time Before I/O Clock 11 I/O Clock Enable Setup Time Before Yx 12 Input Latch or Reg. Hold Time (Yx) 13 Input Latch or Reg. Hold Time (I/O Clock) 14 Output Latch or Reg. Hold Time (Yx) 15 Output Latch or Reg. Hold Time (I/O Clock) 16 Global Clock Enable Hold Time (Yx) 17 Global Clock Enable Hold Time (I/O Clock) 18 I/O Clock Enable Hold Time (Yx) 19 Output Latch or Reg. Clock (from Yx) to Output Delay 20 Input Latch or Register Clock (from Yx) to Output Delay 21 Output Latch or Register Clock (from I/O pin) to Output Delay 22 Input Latch or Register Clock (from I/O pin) to Output Delay 23 Input to Output Enable 24 Input to Output Disable 25 Test OE Output Enable 26 Test OE Output Disable 27 Clock Pulse Duration, High 28 Clock Pulse Duration, Low 29 Register Reset Delay from RESET Low 30 Reset Pulse Width 31 Output Delay Adder for Output Timings Using Slow Slew Rate
12
Specifications ispGDX80VA
External Timing Parameters (Continued)
ispGDX80VA timings are specified with a GRP load (fanout) of four I/O cells. The figure below shows the GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK/CLKEN, MUXsel0-1). Global Clock signals which do not use the GRP have no fanout delay adder.
ispGDX80VA Maximum GRP Delay vs. I/O Cell Fanout
1.6
GRP Delay (ns)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 4 10 20 30 40 50 I/O Cell Fanout 60 70
13
Specifications ispGDX80VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-3 PARAMETER Inputs tio GRP tgrp MUX tmuxd tmuxexp tmuxs tmuxsio tmuxsg tmuxselexp Register tiolat tiosu tioh tioco tior tcesu tceh Data Path tfdbk tiobp tioob tmuxcg tmuxcio tiodg tiodio Outputs tob tobs toeen toedis tgoe ttoe Clocks tioclk tgclk tgclkeng tgclkenio tioclkeng Global Reset tgr 65 Global Reset to I/O Register Latch -- 6.0 -- 11.0 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Input Buffer Delay GRP Delay I/O Cell MUX A/B/C/D Data Delay I/O Cell MUX A/B/C/D Expander Delay I/O Cell Data Select I/O Cell Data Select (I/O Clock) I/O Cell Data Select (Yx Clock) I/O Cell MUX Data Select Expander Delay I/O Latch Delay I/O Register Setup Time Before Clock I/O Register Hold Time After Clock I/O Register Clock to Output Delay I/O Reset to Output Delay I/O Clock Enable Setup Time Before Clock I/O Clock Enable Hold Time After Clock I/O Register Feedback Delay I/O Register Bypass Delay I/O Register Output Buffer Delay I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) I/O Register I/O MUX Delay (Yx Clock) I/O Register I/O MUX Delay (I/O Clock) Output Buffer Delay Output Buffer Delay (Slow Slew Option) I/O Cell OE to Output Enable I/O Cell OE to Output Disable GRP Output Enable and Disable Delay Test OE Enable and Disable Delay I/O Clock Delay Global Clock Delay Global Clock Enable (Yx Clock) Global Clock Enable (I/O Clock) I/O Clock Enable (Yx Clock) DESCRIPTION1 -5 MIN. MAX. MIN. MAX. UNITS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 1.1 1.0 1.5 1.0 1.5 1.5 1.5 1.0 0.8 1.7 1.2 1.0 2.3 0.2 0.6 0.0 0.0 1.5 1.5 3.5 3.5 1.0 4.5 3.5 3.5 0.0 2.5 0.3 1.3 1.5 1.0 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.9 1.1 1.5 2.0 1.5 3.0 2.0 2.0 1.0 2.0 1.5 0.5 1.5 2.0 0.5 0.9 0.0 0.0 2.0 3.0 4.0 5.0 1.5 6.5 4.0 4.0 0.0 2.0 2.0 2.0 2.5 3.5 2.5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
14
Specifications ispGDX80VA
Internal Timing Parameters1
Over Recommended Operating Conditions
-7 PARAMETER Inputs tio GRP tgrp MUX tmuxd tmuxexp tmuxs tmuxsio tmuxsg tmuxselexp Register tiolat tiosu tioh tioco tior tcesu tceh Data Path tfdbk tiobp tioob tmuxcg tmuxcio tiodg tiodio Outputs tob tobs toeen toedis tgoe ttoe Clocks tioclk tgclk tgclkeng tgclkenio tioclkeng Global Reset tgr 65 Global Reset to I/O Register Latch -- 13.7 -- 16.4 ns 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to the Timing Model in this data sheet for further details. # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Input Buffer Delay GRP Delay I/O Cell MUX A/B/C/D Data Delay I/O Cell MUX A/B/C/D Expander Delay I/O Cell Data Select I/O Cell Data Select (I/O Clock) I/O Cell Data Select (Yx Clock) I/O Cell MUX Data Select Expander Delay I/O Latch Delay I/O Register Setup Time Before Clock I/O Register Hold Time After Clock I/O Register Clock to Output Delay I/O Reset to Output Delay I/O Clock Enable Setup Time Before Clock I/O Clock Enable Hold Time After Clock I/O Register Feedback Delay I/O Register Bypass Delay I/O Register Output Buffer Delay I/O Register A/B/C/D Data Input MUX Delay (Yx Clock) I/O Register A/B/C/D Data Input MUX Delay (I/O Clock) I/O Register I/O MUX Delay (Yx Clock) I/O Register I/O MUX Delay (I/O Clock) Output Buffer Delay Output Buffer Delay (Slow Slew Option) I/O Cell OE to Output Enable I/O Cell OE to Output Disable GRP Output Enable and Disable Delay Test OE Enable and Disable Delay I/O Clock Delay Global Clock Delay Global Clock Enable (Yx Clock) Global Clock Enable (I/O Clock) I/O Clock Enable (Yx Clock) DESCRIPTION1 -9 MIN. MAX. MIN. MAX. UNITS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.4 1.1 2.0 2.5 2.0 4.5 2.5 2.5 1.0 3.2 2.3 0.5 1.5 2.5 1.0 1.2 0.3 0.6 2.5 4.5 5.0 7.0 2.2 9.2 6.0 6.0 0.0 2.5 3.2 2.7 3.7 5.7 4.2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.9 1.1 2.5 3.0 2.5 6.0 3.0 3.0 1.0 4.4 2.6 0.5 1.5 2.0 2.0 1.3 0.6 0.7 3.0 6.0 6.0 9.0 2.9 11.9 7.5 7.5 0.0 3.0 4.4 3.4 5.4 8.4 6.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15
Specifications ispGDX80VA
Switching Waveforms
MUXSEL (I/O INPUT) VALID INPUT
DATA (I/O INPUT)
VALID INPUT
tsel
DATA (I/O INPUT) VALID INPUT
tsu
CLK
th tgco tco
tpd
COMBINATORIAL I/O OUTPUT
REGISTERED I/O OUTPUT
Combinatorial Output
1/fmax (external fdbk)
tsuce
OE (I/O INPUT)
CLKEN
tceh
tdis
COMBINATORIAL I/O OUTPUT
ten
Registered Output
I/O Output Enable/Disable
RESET
trw twh
CLK (I/O INPUT)
twl
REGISTERED I/O OUTPUT
trst
Clock Width
Reset
ispGDXVA Timing Model
OE tmuxd #34 tmuxs #36 tmuxio #37 tmuxg #38 tmuxcg #50 tmuxcio #51 tgoe #58
MUX Expander Input A B C D MUX0 GRP MUX1
tmuxexp #35 tmuxselexp #39
MUX Expander Output
TOE
ttoe #59 tiobp #48
D CLKEN CLK
Q
tioob #49 tob #54 tobs #55 toeen #56 toedis #57
I/O Pin
tgrp #33 tiod #52, #53
tiolat #40 tiosu #41 tioh #42 tioco #43 tior #44 tcesu #45 tceh #46
tgr #65
RESET
tfdbk #47 tio #32 CLKEN CLK tioclkeg #64 tioclk #60
Y0,1,2,3
tgclk #61
Y0,1,2,3, Enable
0902/gdxv/va
tgclkeng #62 tgclkenio #63
16
Specifications ispGDX80VA
ispGDX Development System
The ispGDX Development System supports ispGDX design using a simple language syntax and an easy-touse Graphical User Interface (GUI) called Design Manager. From creation to In-System Programming, the ispGDX system is an easy-to-use, self-contained design tool delivered on CD-ROM media. Status Bar and the work area. The figure below shows these elements of the ispGDX GUI. The Menu Bar displays topics related to functions used in the design process. Access the various drop-down menus and submenus by using the mouse or "hot" keys. The menu items available in the ispGDX system are FILE, EDIT, DEVICE, INVOKE, INTERFACES, VIEW, WINDOW and HELP. The Tool Bar is a quick and easy way to perform many of the functions found in the menus with a single click of the mouse. File, Edit, Undo, Redo, Find, Print Download and Compiler are just some of the Icons found in the ispGDX Tool Bar. For instance, the Compiler Icon performs the same function as the Invoke => Compiler menu commands, including design analysis and rule checking and the fitting operation. The Status Bar displays action prompts and the line and column numbers reflect the location of the cursor within the message window or the work area.
Features
* Easy-to-use Text Entry System * ispGDX Design Compiler - Design Rule Checker - I/O Connectivity Checker - Automatic Compiler Function * Industry Standard JEDEC File for Programming * Min / Max Timing Report * Interfaces To Popular Timing Simulators * User Electronic Signature (UES) Support * Detailed Log and Report Files For Easy Design Debug * On-Line Help * Windows(R) 3.1x, Windows 95, Windows 98 and Windows NT(R) Compatible Graphical User Interface * SUN O/S, Command Line Driven version available
Workstation Version
The ispGDX software is also available for use under the Sun O/S 4.1.x or Solaris 2.4 or 2.5. The Sun version of the ispGDX software is invoked from the command line under the UNIX operating system. A GUI is not supported in this environment. In the UNIX environment, the ispGDX Design File (GDF) must be created using a text editor. Once the GDF has been created, invoke the ispGDX workstation software from the UNIX command line. The following is an example of how to invoke ispGDX software. Usage: ispGDX [-i input_file] [-of[edif|orcad|viewlogic|verilog|vhdl]] [-p part name] [-r par_file] Where: -i input_file -of [edif | orcad | viewlogic | verilog | vhdl] -p part_name -r par_file ispGDX design file Output format ispGDX part number Read parameters from parameter file
PC Version
With the ispGDX GUI for the PC, command line entry is not required. The tools run under Microsoft Windows 3.1, Windows 95, Windows 98 and Windows NT. When the ispGDX software is invoked, the Design Manager and an accompanying message window are displayed. The Design Manager consists of the Menu Bar, Tool Bar, Lattice's ispGDX Development System Interface
17
Specifications ispGDX80VA
ispGDX Development System (Continued) The GDF File
The GDF file is a simple text description of the design function, device and pin parameters. The file has four parts: device selection, set and constant statements, a pin section and a connection section. A sample file looks like this: // 32-Bit Data 3 to 1 Mux DESIGN datamux; This example shows a simple, but complete, 32-bit 3:1 MUX design. Once completed, the compiler takes over.
Powerful Syntax
Lattice's ispGDX Design System uses simple, but powerful, syntax to easily define a design. The !(bang) operator controls pin polarity and can be used in both the pin and connection sections of the design definition. Dot extensions define data inputs, select controls for the 4:1 multiplexor, and control inputs of sequential elements and tri-state buffers. Dot extensions are .M# (MUX Input), .S# (MUX Select), and control functions, such as .CLK, .EN, .OE and .A (shown in adjacent table). Pin Attributes are assigned in the pin section of the GDF as well. SLOWSLEW selects the slow slew rate for an output buffer. The Pull parameter can be used to select the internal pull-up or bus hold latch. OPEN drain can be used to select open drain operation. The COMB attribute distinguishes the structure for bidirectional pins. If COMB is used, the input register, or latch, of an output buffer will be applied to bidirectional pins. Please consult the ispGDX Development System Manual for full details. ispGDX GDF File Dot Extensions
Type Dot Ext. .M0 MUX Input .M1 .M2 .M3 .S0 .S1 .CLK .EN Description MUXA Data input to 4:1 MUX MUXB Data input to 4:1 MUX MUXC Data Input to 4:1 MUX MUXD Data input to 4:1 MUX MUX0 Selection input to 4:1 MUX MUX1 Selection input to 4:1 MUX Clock for a register Latch enable for a latch signal Output enable for 3-state output or bidirectional signal Clock enable for register clock Adjacent MUX output of an I/O cell
ispGDXV Dot Ext
PART ispGDX160V-7Q208; PARAM SECURITY ON; PARAM OPENDRAIN ON; PARAM PULL HOLD;
// // // //
USE OPEN DRAIN OPTION USE BUS HOLD LATCH OPTION
SET SET SET SET
BUS_A BUS_B BUS_C BUS_D
[dataA31..dataA0]; [dataB31..dataB0]; [dataC31..dataC0]; [dataD31..dataD0]; {A31..A0}; {B31..B0}; {C31..C0}; {D31..D0};
INPUT INPUT INPUT OUTPUT
BUS_A BUS_B BUS_C BUS_D
INPUT [oe] {B37}; INPUT [clk] {B36}; INPUT [sel1] INPUT [sel0] BEGIN BUS_D.m0 BUS_D.m1 BUS_D.m2 BUS_D.m3 = = = = BUS_A; BUS_B; BUS_C; VCC; {B38}; {B39};
MUX Selection
Control
.OE .CE
// Default all // outputs to VCC
MUX Output
.A
BUS_D.s1 = sel1; BUS_D.s0 = sel0; BUS_D.oe = oe; BUS_D.clk = clk; END
18
Specifications ispGDX80VA
ispGDX Development System (Continued) The ispGDX Design System Compiler
After the GDF file is created, the compiler checks the syntax and provides helpful hints and the location of any syntax errors. The compiler performs design rule checks, such as, clock and enable designations, the use of input/ output/BIDI usage, and the proper use of attributes. I/O connectivity is also checked to ensure polarity, MUX selection controls, and connections are properly made. Compilation is completed automatically and report and programming files are saved.
Third-Party Timing Simulation
The ispGDX Design System will generate simulation netlists as specified by a user. The simulation netlist formats available are: EDIF, Verilog (OVI compliant), VHDL (VITAL compliant), Viewlogic, and OrCAD. For In-System Programming, Lattice's ispGDX devices may be programmed, alone or in a chain with up to 100 other Lattice ISP devices, using Lattice's ISP Daisy Chain Download software. This powerful Windows-based tool can be launched from the Tool Bar or by Invoking the Download option from the drop down menu within the ispGDX Design System. ISP Daisy Chain Download version 7.1 or above supports the ispGDX Family devices.
Reports Generated
When the ispGDX system compiles a design and generates the specified netlists, the following output files are created: Report Files: .log Compiler History .rpt Compiler Report .mfr Maximum Frequency Timing Report .tsu Set-up and Hold Timing Report .tco Clock to Out Timing Report .tpt Timing Report Simulation File: .sim Post-Route Simulation With LAC Format Netlists: .edo .vlo .ifo .vho .vhn .vto EDIF Output Verilog Output OrCAD Output VHDL non-VITAL with Maximum Delays Output VHDL non-VITAL with Maximum Delays Output VHDL VITAL Output
Download: .jed JEDEC Device Programming File
19
Specifications ispGDX80VA
In-System Programmability
All necessary programming of the ispGDXVA is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. On-chip programming can be accomplished using an IEEE 1149.1 boundary scan protocol. The IEEE 1149.1compliant interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control. The EPEN pin is also used to enable or disable the JTAG port. The embedded controller port enable pin (EPEN) is used to enable the JTAG tap controller and in that regard has similar functionality to a TRST pin. When the pin is driven high, the JTAG TAP controller is enabled. This is also true Figure 9. ispJTAG Device Programming Interface
TDO TDI TMS TCK EPEN ispJTAG Programming Interface
when the pin is left unconnected, in which case the pin is pulled high by the permanent internal pullup. This allows ISP programming and BSCAN testing to take place as specified by the Instruction Table. When the pin is driven low, the JTAG TAP controller is driven to a reset state asynchronously. It stays there while the pin is held low. After pulling the pin high the JTAG controller becomes active. The intent of this feature is to allow the JTAG interface to be directly controlled by the data bus of an embedded controller (hence the name Embedded Port Enable). The EPEN signal is used as a "device select" to prevent spurious programming and/or testing from occuring due to random bit patterns on the data bus. Figure 9 illustrates the block diagram for the ispJTAG interface.
ispGDX 80VA Device
ispLSI Device
ispMACH Device
ispGDX 80VA Device
ispGDX 80VA Device
20
Specifications ispGDX80VA
Boundary Scan
The ispGDXVA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface. The boundary scan circuitry on the ispGDXVA Family operates independently of the programmed pattern. This Figure 10. Boundary Scan Register Circuit for I/O Pins
HIGHZ
allows customers using boundary scan test to have full test capability with only a single BSDL file. The ispGDXVA devices are identified by the 32-bit JTAG IDCODE register. The device ID assignments are listed in Table 4.
EXTEST SCANIN (from previous cell
BSCAN Registers BSCAN Latches TOE Normal Function OE 0 1
D
Q
D
Q
EXTEST PROG_MODE
Normal Function
0
I/O Pin
1
D
Q
D
Q
D
Q
SCANOUT (to next cell)
Shift DR
Clock DR
Update DR
Reset
Table 3. I/O Shift Register Order
DEVICE ispGDX80VA I/O SHIFT REGISTER ORDER TDI, TOE, RESET, Y1, Y0, I/O B10 .. B19, I/O C0 .. C19, I/O D0 .. D9, I/O B9 .. B0, I/O A19.. A0, I/O D19 .. D10, TDO
I/O Shift Reg Order/ispGDXVA
Table 4. ispGDX80VA Device ID Codes
DEVICE ispGDX80VA 32-BIT BOUNDARY SCAN ID CODE 0001, 0000, 0011, 0101, 0000, 0000, 0100, 0011
ID Code/GDX80VA
21
Specifications ispGDX80VA
Boundary Scan (Continued)
The ispJTAG programming is accomplished by executing Lattice private instructions under the Boundary Scan State Machine. Details of the programming sequence are transparent to the user and are handled by Lattice ISP Daisy Chain Figure 11. Boundary Scan Register Circuit for Input-Only Pins Downlowad (ispDCDTM), ispCODE `C' routines or any third-party programmers. Contact Lattice Technical Support to obtain more detailed programming information.
Input Pin SCANIN (from previous cell Shift DR Clock DR D Q SCANOUT (to next cell)
Figure 12. Boundary Scan State Machine
1 Test-Logic-Reset 0 1 Run-Test/Idle
0
Select-DR-Scan 0 1 Capture-DR 0 Shift-DR 0 1 Exit1-DR 1 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0
1
1 Select-IR-Scan 0 1 Capture-IR 0 Shift-IR 0 1 Exit1-IR 1 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0
22
Specifications ispGDX80VA
Boundary Scan (Continued)
Figure 13. Boundary Scan Waveforms and Timing Specifications
TMS
TDI Tbtsu Tbtch TCK Tbtcl Tbth Tbtcp
Tbtvo TDO Valid Data
Tbtco Valid Data
Tbtoz
Tbtcsu Data to be captured
Tbtch Data Captured
Tbtuov Data to be driven out
Tbtuco Valid Data
Tbtuoz Valid Data
Symbol tbtcp tbtch
tbtcl tbtsu tbth trf tbtco tbtoz tbtvo tbtcpsu tbtcph tbtuco tbtuoz tbtuov
Parameter TCK [BSCAN test] clock pulse width TCK [BSCAN test] pulse width high TCK [BSCAN test] pulse width low TCK [BSCAN test] setup time TCK [BSCAN test] hold time TCK [BSCAN test] rise and fall time TAP controller falling edge of clock to valid output TAP controller falling edge of clock to data output disable TAP controller falling edge of clock to data output enable BSCAN test Capture register setup time BSCAN test Capture register hold time BSCAN test Update reg, falling edge of clock to valid output BSCAN test Update reg, falling edge of clock to output disable BSCAN test Update reg, falling edge of clock to output enable
Min 100 50 50 20 25 50 - - - 20 25 - - -
Max - - - - - - 25 25 25 - - 50 50 50
Units ns ns ns ns ns mV/ns ns ns ns ns ns ns ns ns
23
Specifications ispGDX80VA
Signal Descriptions
Signal Name I/O Description Input/Output Pins - These are the general purpose bidirectional data pins. When used as outputs, each may be independently latched, registered or tristated. They can also each assume one other control function (OE, CLK/CLKEN, and MUXsel as described in the text). This pin can be configured by the user through software to act as a RESET pin or as an I/O (I/O D10) The default is RESET. If programmed to act as RESET, this pin is an active LOW Input Pin and resets all I/O Register outputs when LOW. Input Pins - These can be either Global Clocks or Clock Enables. In addition, Y1 is multiplexed with TOE. Each pin can drive any or all I/O cell registers. The Test Output Enable (TOE) pin tristates all I/O pins when LOW Input Pin - JTAG TAP Controller Enable Pin. When high, JTAG operation is enabled. When low, JTAG TAP controller is driven to reset. Input Pin - Serial data input during ISP programming or Boundary Scan mode. Input Pin - Serial data clock during ISP programming or Boundary Scan mode. Input Pin - Control input during ISP programming or Boundary Scan mode. Output Pin - Serial data output during ISP programming or Boundary Scan mode. Ground (GND) Vcc - Supply voltage (3.3V). Input - This pin is used if optional 2.5V output is to be used. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the VCC supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply.
RESET / I/O D10
Y1/CLKEN1/TOE, Y0/CLKEN0 EPEN TDI TCK TMS TDO GND VCC VCCIO
24
Specifications ispGDX80VA
Signal Locations: ispGDX80VA
Signal RESET /I/O D10 Y0/CLKEN0 EPEN TDI TCK TMS TDO GND VCC VCCIO 90 38 35 39 36 86 85 6, 18, 29, 45, 56, 68, 79, 95 12, 37, 62, 88 89 100-Pin TQFP
Y1/CLKEN1/TOE 87
I/O Locations: ispGDX80VA
I/O Signal I/O A0 I/O A1 I/O A2 I/O A3 I/O A4 GND I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 VCC I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 GND I/O A15 I/O A16 I/O A17 I/O A18 I/O A19 I/O B0 Control Signal CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK 100 TQFP 1 2 3 4 5 7 8 9 10 11 13 14 15 16 17 19 20 21 22 23 24 I/O Signal I/O B1 I/O B2 I/O B3 I/O B4 GND I/O B5 I/O B6 I/O B7 I/O B8 I/O B9 VCC I/O B10 I/O B11 I/O B12 I/O B13 I/O B14 GND I/O B15 I/O B16 I/O B17 I/O B18 I/O B19 I/O C0 I/O C1 Control Signal OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE 100 TQFP 25 26 27 28 30 31 32 33 34 40 41 42 43 44 46 47 48 49 50 51 52 I/O Signal I/O C2 I/O C3 I/O C4 GND I/O C5 I/O C6 I/O C7 I/O C8 I/O C9 VCC I/O C10 I/O C11 I/O C12 I/O C13 I/O C14 GND I/O C15 I/O C16 I/O C17 I/O C18 I/O C19 I/O D0 I/O D1 I/O D2 Control Signal MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 100 I/O TQFP Signal 53 54 55 57 58 59 60 61 63 64 65 66 67 69 70 71 72 73 74 75 76 I/O D3 I/O D4 GND I/O D5 I/O D6 I/O D7 I/O D8 I/O D9 VCC VCCIO I/O D10* I/O D11 I/O D12 I/O D13 I/O D14 GND I/O D15 I/O D16 I/O D17 I/O D18 I/O D19 Control Signal MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE 100 TQFP 77 78 80 81 82 83 84
MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2
90 91 92 93 94 96 97 98 99 100
*I/O D10 is multiplexed with RESET. The functionality is programmable and selected through software. Note: VCC and GND Pads Shown for Reference
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Specifications ispGDX80VA
Pin Configuration: ispGDX80VA
ispGDX80VA 100-Pin TQFP Pinout Diagram
MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1
Control Data
I/O D19 I/O D18 I/O D17 I/O D16 I/O D15 GND I/O D14 I/O D13 I/O D12 I/O D11 RESET/I/O D10 VCCIO VCC Y1/CLKEN1/TOE TMS TDO I/O D9 I/O D8 I/O D7 I/O D6 I/O D5 GND I/O D4 I/O D3 I/O D2
Control CLK OE MUXsel1 MUXsel2 CLK
OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE MUXsel1 MUXsel2 CLK OE
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
Data
I/O A0 I/O A1 I/O A2 I/O A3 I/O A4 GND I/O A5 I/O A6 I/O A7 I/O A8 I/O A9 VCC I/O A10 I/O A11 I/O A12 I/O A13 I/O A14 GND I/O A15 I/O A16 I/O A17 I/O A18 I/O A19 I/O B0 I/O B1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Data
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O D1 I/O D0 I/O C19 I/O C18 I/O C17 I/O C16 I/O C15 GND I/O C14 I/O C13 I/O C12 I/O C11 I/O C10 VCC I/O C9 I/O C8 I/O C7 I/O C6 I/O C5 GND I/O C4 I/O C3 I/O C2 I/O C1 I/O C0
Control
OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK MUXsel2 MUXsel1 OE CLK
ispGDX80VA
Top View
Data I/O B2 I/O B3 I/O B4 GND I/O B5 OE I/O B6 MUXsel1 I/O B7 MUXsel2 I/O B8 CLK I/O B9 OE EPEN TCK VCC Y0/CLKEN0 TDI I/O B10 MUXsel1 I/O B11 MUXsel2 I/O B12 CLK I/O B13 OE I/O B14 MUXsel1 GND I/O B15 MUXsel2 I/O B16 CLK I/O B17 OE I/O B18 MUXsel1 I/O B19 MUXsel2 Control MUXsel1 MUXsel2 CLK
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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Specifications ispGDX80VA
Part Number Description
ispGDX 80VA
Device Family Device Number Speed 3 = 3.5ns Tpd 5 = 5.0ns Tpd 7 = 7.0ns Tpd 9 = 9.0ns Tpd
X XXXX X
Grade Blank = Commercial I = Industrial Package T100 = 100-Pin TQFP
0212/gdx80VA
Ordering Information
COMMERCIAL
FAMILY ispGDXVA tpd (ns) 3.5 5 7 ORDERING NUMBER ispGDX80VA-3T100 ispGDX80VA-5T100 ispGDX80VA-7T100 PACKAGE 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP
Table 2-0041A/gdx80VA
INDUSTRIAL
FAMILY ispGDXVA tpd (ns) 5 7 9 ORDERING NUMBER ispGDX80VA-5T100I ispGDX80VA-7T100I ispGDX80VA-9T100I PACKAGE 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP
Table 2-0041/gdx80VA
Note: The ispGDX80VA devices are dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster, e.g. ispGDX80VA-3T100-5I.
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